Babar khan

Babar khan

Electrical Engineer | PhD Candidate | Software-Hardware Developer

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Posts

Our ACM Transaction on Storage (TOS) journal (manuscript) mentioned in esteemed Storage Newsletter

less than 1 minute read

Published:

Since I have been working in the field of storage as a researcher and practitioner, we recently contributed a comprehensive scientific paper titled “Reflecting on the Past 17 Years of Shingled Magnetic Recording for Insights into Future Disk Transitions” to the Special Issue of ACM Transactions on Storage (TOS). The SI was titled “The Past, Present, and Future of Storage Technologies”. Read more

Feels good to be mentioned in HPCwire: Global News on High Performance Computing (HPC)

1 minute read

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In 2023, I had attended the in-person International Conference for High Performance Computing, Networking, Storage, and Analysis (commonly known as SC 2023) in Denver, Colorado, USA. Being November in Denver, the weather was as expected—cold but sunny (my kind of weather). SC is always a week-long event, and since I arrived a day or two before the official start, I decided to collect my badge early to avoid the long queues on opening day. After picking up my badge, I thought, why not take a walk around the Colorado Convention Center as a warm-up for the upcoming conference days? While exploring the area, I noticed some talks taking place in one of the halls at the Convention Center. Read more

Infineon Quantum Computing Winter School 2024

less than 1 minute read

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I have not been involved in Quantum Computing research topics, but like most researchers (read PhD candidate) in Computer Science and software-hardware engineer, I have been intrigued by the topic. Attending SC 2023 in Denver, Colorado, USA, was icing on the cake where QC was a dominating topic both in research and industrial tracks. Luckily the stars aligned and I had an opportunity to attend virtually Quantum Computing (QC) Winter School 2024 in February 2024 by Infineon. Infineon Technologies AG is Germany’s largest semiconductor manufacturer. Read more

NVIDIA AI Instructor led Training: Building Transformer-Based Natural Language Processing Applications

less than 1 minute read

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To stay well-informed about the scientific (fine-granular) aspects of Artificial Intelligence, I took the opportunity to enroll in an instructor-led training program titled “Building Transformer-Based Natural Language Processing Applications.” Through this training, I acquired knowledge on utilizing Transformer-based natural language processing models for tasks like text classification, including the categorization of documents. Additionally, I learned how to harness Transformer-based models for tasks such as named-entity recognition (NER). The training equipped me with the skills to analyze different model features, constraints, and characteristics, enabling me to determine the most suitable model for a specific use case based on metrics, domain specificity, and available resources. Read more

In my hand: The new Seagate HAMR disk at SC 2023 exhibition, Denver, Colorado, USA

less than 1 minute read

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Last week, I attended SC 2023 in Denver, Colorado, USA. The SC Conference brought together a vast assembly of participants, numbering 14 thousand this year, from the international high-performance computing community. It served as a nexus for scientists, engineers, researchers, educators, programmers, system administrators, and developers worldwide. Simultaneously, SC provided manufacturers, vendors, research institutions, and HPC service providers with a venue in the form of an exhibition. This year’s event featured approximately 438 exhibitors, among them Seagate. Read more

CISPA 2023 System Security event in-person, Saarland, Germany, 2023

less than 1 minute read

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Thanks to the travel grant, I had an opportunity to attend CISPA 2023 in August 2023. The CISPA Helmholtz Center for Information Security is a German national Big Science Institution within the Helmholtz Association. Their research encompasses all aspects of Information Security. This year‘s international CISPA Summer School had a focus on System Security with one week of talks, hands-on sessions, discussions, and a social program such as a pub quiz. The event included sessions by 8 invited speakers and 5 CISPA Faculty. Read more

DevConf 2023 in-person, Brno, Czech Republic

less than 1 minute read

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During my PhD I have been working on topics related to Linux operating system (to be precise Linux storage) and open source projects. This compelled me to attend in-person DevConf.CZ in Brno, Czech Republic 2023 that is annual, free, Red Hat sponsored community conference for developers, admins, DevOps engineers, testers, documentation writers and other contributors to open source technologies. Although it was a three days event with a very interesting itinerary of technical talks, below is the list of some of the talks relevant to my research and everyday tasks: Read more

Dan Kohn Scholarship for KubeCon + CloudNativeCon North America 2022, Detroit, USA

less than 1 minute read

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The Cloud Native Computing Foundation (CNCF) is a Linux Foundation project that was founded in 2015 to help advance container technology and align the tech industry around its evolution. It was announced alongside Kubernetes 1.0, an open source container cluster manager, which was contributed to the Linux Foundation by Google as a seed technology. Founding members include Google, CoreOS, Mesosphere, Red Hat, Twitter, Huawei, Intel, Cisco, IBM, Docker, Univa, and VMware.[2][3] Today, CNCF is supported by over 450 members. Since cloud and storage is part of my research, I was lucky to attend KubeCon 2022 in-person in Detroit, USA. Read more

Xilinx XACC Winter school 2021

less than 1 minute read

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Xilinx, Inc. is an American semiconductor company that is primarily a supplier of programmable logic devices. The company invented the Field-programmable gate array (FPGA). Yes, you read it correctly, The FPGA ! Considering the rapid growth of FPGAs accelerators in data-centers and various other fields, it is not easy to keep up the pace with the knowledge base of modern FPGAs. These bleeding-edge FPGAs are complex and programming them is a hard-problem. Recently Xilinx was gracious enough to organize a Winter School 2021 primarily for PhD researchers who use FPGA and its tool in their research. It was a 5-day school with technical presentations, talks and a project work. The project work was really interesting as we had to use open-source Vitis libraries for the first time. Read more

Data Parallel C++ brief book review and recommendation (Part 1)

3 minute read

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Bjarne Stroustrup has written in one of his books that “Our civilization runs on software”. Hence writing on anything related to software is itself part of learning for me. One such topic is parallel programming which is making inroads in super computing (SC) domain. The SC conference series 2020 has been once again full of tutorials, workshops and novel research papers. As a researcher involved in accelerating algorithms I’m interested in reading different technical books. Read more

portfolio

publications

talks

Hardware-Aided Trusted Computing in High-Level Synthesis (HLS) for FPGAs

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Hardware accelerators are being increasingly integrated into today’s heterogenous computing systems to achieve improved performance. However, the resulting heterogenous hardware also increases the challenge to ensure the security of these accelerators. High-Level Synthesis (HLS) automates the creation of a register transfer level (RTL) description of a digital circuit starting from its high-level specification (e.g., C/C++/SystemC). In this talk, I would like to discuss different extensions and methodologies to High-Level Synthesis (HLS) compilers for generating secure accelerators. Precisely addressing the HLS vulnerabilities like side-channel listed in Common Weakness Enumeration (CWE) list. Read more

Modern C++, Embedded Linux and FPGAs: A match made in heaven

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FPGAs in general are notorioulsy famous for having a difficult programming model. Given that, there has been a growing focus to design FPGA hardware at a higher level of abstraction through high-level languages. Modern C++ is clearly a winner in this case. The last four C++ standards have come a long way to make C++ language even more compatible with embedded sytems. Many open source FPGA libraries are based on modern C++. Similarly, almost every open-source high-level synthesis (HLS) compiler for FPGA is either based on GCC or LLVM/Clang. This talk will show how a modern C++ developer can adopt certain coding practises to fully exploit the underlying spatial parallelism of FPGA hardware. Read more

LLVM and ANTLR: A Starter on a non-Linux Machine

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Although Linux is still the best preferred operating system, the talk begins with a problem statement regarding the dependencies of ANTLR and LLVM on Windows. To this end, the presenter will explain how these dependency issues can be resolved through an easy-to-use environment for building, installing and running native LLVM and ANTLR on Windows. Furthermore, the talk will briefly explain how we can design domain specific languages (DSLs) using a powerful combination of ANTLR and LLVM front end while maintaining a logical isolation of parsing and code generation. Read more

One stop shop: Best Practices for Programming Embedded FPGAs

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FPGAs are increasingly being used in today’s embedded systems. But they are notoriously complex for having a difficult programming model. In order to counter this complexity, there has been a growing focus to design FPGA hardware at a higher level of abstraction with new languages and compilers. This talk will serve as “one stop shop” for topics related to these developments. Read more

FPGA 101 for Embedded C++ Developers

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Many say that FPGAs are the new motherboards. And I have been working on compiling best coding practices to develop designs on FPGAs through C++. Therefore this talk is a continuation of my on going work regarding these best coding practices. If you are a C++ developer and you want to develop designs for FPGA through C++ explicitly, this talk will cover essential coding practices for you. Read more

DeLiBA: An Open-Source Hardware/Software Framework for the Development of Linux Block I/O Accelerators

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This talk titled “DeLiBA: An Open-Source Hardware/Software Framework for the Development of Linux Block I/O Accelerators” was part of FPGA design track of FPL 2022 conference. The International Conference on Field-Programmable Logic and Applications (FPL) was the first and remains the largest conference covering the rapidly growing area of field-programmable logic and reconfigurable computing. During the past 31 years, many of the advances in reconfigurable system architectures, applications, embedded processors, design automation methods and tools were first published in the proceedings of the FPL conference series. The conference objective is to bring together researchers and practitioners from both academia and industry and from around the world. Read more

Accelerating the HPC I/O for Low Latency and High Throughput with 16-nanometer FPGA-based Hardware Accelerators

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The existing HPC I/O stack struggles with the growing demands of HPC scientific workloads. To start with the latency bottleneck, there is a deeply layered kernel hierarchy to translate HPC I/O requests to the actual storage operations. This layered architecture adds a significant overhead along the entire I/O request path. Measurements have shown that it takes between 18,000 and 20,000 instructions to send and receive a single fundamental 4KB I/O request. Our novel hardware/software framework, named DeLiBA, aims to bridge this gap by facilitating the evelopment of software components within the HPC I/O stack in user space, rather than the kernel space, and leverages a proven 16 nanometer (nm) FPGA framework to quickly deploy the FPGA-based HPC I/O accelerators. Our initial results achieve a 10% increase in throughput and demonstrates up to 2.3 times the I/O operations per second compared to conventional methods. Read more

Emerging Heterogeneous Computing Architectures Every Software Engineer Should Know (Compilers and DSLs)

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This talk was given in-person at Research in Software Engineering Germany Chapter namely “deRSE” in Würzburg, Germany 2024. Following is the abstract of the talk Software engineers communicate with hardware through a language known as an instruction set architecture (ISA). However, the conclusion of Dennard scaling and Moore’s Law implies that complex heterogeneous ISAs are replacing this traditional ISA. In light of this, the expertise required to develop new compilers and create domain-specific languages will be crucial for future software engineers. Therefore, this talk will address the challenges posed by emerging computing architectures and research related to abstracting the complex ISA. As a use case, the talk will present an open-source tool that recently received the Best Paper Award at one of the leading computer architecture conferences. Read more

A Sneak Peek into Quantum Compilers and Embedded Systems

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This talk will briefly explain the current landscape of quantum computing, focusing on the quantum computing compilers that enable efficient quantum algorithms implementation in the embedded systems. To this end, the talk will explicitly focus on C++ code snippets to showcase optimization techniques and highlight compiler-specific features.cenario carefully. Having gathered a couple interesting instances of such examinations and their findings, we would love to present them! Read more

Speeding-up Hardware-Accelerated Distributed Storage Access by Tighter Linux Kernel Integration and Use of a Modern API

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This talk presents an open-source Linux block I/O storage framework called “DeLiBA-K” that leverages FPGA to accelerate block storage operations in data centers. Notably, DeLiBA-K is the first storage research framework to integrate Linux new asynchronous I/O interface, “io_uring”, into an FPGA-based framework. Since DeLiBA-K uses an open-source distributed storage called Ceph as a use case, it delivers better speed-ups compared to contemporary Ceph I/O hardware accelerators. These speed-ups have been rigorously tested and validated in an industrial environment with real-world workloads. Read more

teaching

Teaching experience 1

Undergraduate course, University 1, Department, 2014

This is a description of a teaching experience. You can use markdown like any other post. Read more

Teaching experience 2

Workshop, University 1, Department, 2015

This is a description of a teaching experience. You can use markdown like any other post. Read more