Talks and presentations

Speeding-up Hardware-Accelerated Distributed Storage Access by Tighter Linux Kernel Integration and Use of a Modern API

November 22, 2024

SC 2024, Atlanta, Georgia, USA, This talk was given at SuperComputing conference 2024, Atlanta, Georgia, USA

This talk presents an open-source Linux block I/O storage framework called “DeLiBA-K” that leverages FPGA to accelerate block storage operations in data centers. Notably, DeLiBA-K is the first storage research framework to integrate Linux new asynchronous I/O interface, “io_uring”, into an FPGA-based framework. Since DeLiBA-K uses an open-source distributed storage called Ceph as a use case, it delivers better speed-ups compared to contemporary Ceph I/O hardware accelerators. These speed-ups have been rigorously tested and validated in an industrial environment with real-world workloads.

A Sneak Peek into Quantum Compilers and Embedded Systems

March 15, 2024

emBO++ 2024, Bochum, Germany, This talk was given in-person at embO++ 2024 in Bochum, Germany, on 15th March 2024, Bochum, Germany

This talk will briefly explain the current landscape of quantum computing, focusing on the quantum computing compilers that enable efficient quantum algorithms implementation in the embedded systems. To this end, the talk will explicitly focus on C++ code snippets to showcase optimization techniques and highlight compiler-specific features.cenario carefully. Having gathered a couple interesting instances of such examinations and their findings, we would love to present them!

Emerging Heterogeneous Computing Architectures Every Software Engineer Should Know (Compilers and DSLs)

March 06, 2024

deRSE24 - Conference for Research Software Engineering in Germany 2024, This talk was given in-person at Research in Software Engineering Germany Chapter namely deRSE in Wuerzburg, Germany, on 6th March 2024, Julius-Maximilians-University Wuerzburg, Germany

This talk was given in-person at Research in Software Engineering Germany Chapter namely “deRSE” in Würzburg, Germany 2024. Following is the abstract of the talk Software engineers communicate with hardware through a language known as an instruction set architecture (ISA). However, the conclusion of Dennard scaling and Moore’s Law implies that complex heterogeneous ISAs are replacing this traditional ISA. In light of this, the expertise required to develop new compilers and create domain-specific languages will be crucial for future software engineers. Therefore, this talk will address the challenges posed by emerging computing architectures and research related to abstracting the complex ISA. As a use case, the talk will present an open-source tool that recently received the Best Paper Award at one of the leading computer architecture conferences.

Accelerating the HPC I/O for Low Latency and High Throughput with 16-nanometer FPGA-based Hardware Accelerators

November 13, 2023

The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC) 2023, This talk was given in-person at Super Computing (SC) 2023 conference in Denver, Colorado, USA, Nov, 2023, Denver, Colorado, USA

The existing HPC I/O stack struggles with the growing demands of HPC scientific workloads. To start with the latency bottleneck, there is a deeply layered kernel hierarchy to translate HPC I/O requests to the actual storage operations. This layered architecture adds a significant overhead along the entire I/O request path. Measurements have shown that it takes between 18,000 and 20,000 instructions to send and receive a single fundamental 4KB I/O request. Our novel hardware/software framework, named DeLiBA, aims to bridge this gap by facilitating the evelopment of software components within the HPC I/O stack in user space, rather than the kernel space, and leverages a proven 16 nanometer (nm) FPGA framework to quickly deploy the FPGA-based HPC I/O accelerators. Our initial results achieve a 10% increase in throughput and demonstrates up to 2.3 times the I/O operations per second compared to conventional methods.

DeLiBA: An Open-Source Hardware/Software Framework for the Development of Linux Block I/O Accelerators

August 30, 2022

FPGA Design track track at 33rd International Conference on Field-Programmable Logic and Applications (FPL) 2022, This talk was given in the FPGA Design track of 33rd International Conference on Field-Programmable Logic and Applications (FPL) 2022, Belfast, United Kingdom

This talk titled “DeLiBA: An Open-Source Hardware/Software Framework for the Development of Linux Block I/O Accelerators” was part of FPGA design track of FPL 2022 conference. The International Conference on Field-Programmable Logic and Applications (FPL) was the first and remains the largest conference covering the rapidly growing area of field-programmable logic and reconfigurable computing. During the past 31 years, many of the advances in reconfigurable system architectures, applications, embedded processors, design automation methods and tools were first published in the proceedings of the FPL conference series. The conference objective is to bring together researchers and practitioners from both academia and industry and from around the world.

FPGA 101 for Embedded C++ Developers

March 25, 2022

Long session of 36 minutes, This talk is a part of the embedded systems conference emBO++ year 2022, Bochum, Germany

Many say that FPGAs are the new motherboards. And I have been working on compiling best coding practices to develop designs on FPGAs through C++. Therefore this talk is a continuation of my on going work regarding these best coding practices. If you are a C++ developer and you want to develop designs for FPGA through C++ explicitly, this talk will cover essential coding practices for you.

One stop shop: Best Practices for Programming Embedded FPGAs

February 05, 2022

Devroom Talk, FOSDEM 2022, Belgium

FPGAs are increasingly being used in today’s embedded systems. But they are notoriously complex for having a difficult programming model. In order to counter this complexity, there has been a growing focus to design FPGA hardware at a higher level of abstraction with new languages and compilers. This talk will serve as “one stop shop” for topics related to these developments.

LLVM and ANTLR: A Starter on a non-Linux Machine

February 05, 2022

Devroom Talk, FOSDEM 2022, Belgium

Although Linux is still the best preferred operating system, the talk begins with a problem statement regarding the dependencies of ANTLR and LLVM on Windows. To this end, the presenter will explain how these dependency issues can be resolved through an easy-to-use environment for building, installing and running native LLVM and ANTLR on Windows. Furthermore, the talk will briefly explain how we can design domain specific languages (DSLs) using a powerful combination of ANTLR and LLVM front end while maintaining a logical isolation of parsing and code generation.

Modern C++, Embedded Linux and FPGAs: A match made in heaven

October 04, 2021

Long session, The South African Linux and Open Source conference 2021, South Africa

FPGAs in general are notorioulsy famous for having a difficult programming model. Given that, there has been a growing focus to design FPGA hardware at a higher level of abstraction through high-level languages. Modern C++ is clearly a winner in this case. The last four C++ standards have come a long way to make C++ language even more compatible with embedded sytems. Many open source FPGA libraries are based on modern C++. Similarly, almost every open-source high-level synthesis (HLS) compiler for FPGA is either based on GCC or LLVM/Clang. This talk will show how a modern C++ developer can adopt certain coding practises to fully exploit the underlying spatial parallelism of FPGA hardware.

Hardware-Aided Trusted Computing in High-Level Synthesis (HLS) for FPGAs

February 05, 2021

Devroom Talk, FOSDEM 2021, Belgium

Hardware accelerators are being increasingly integrated into today’s heterogenous computing systems to achieve improved performance. However, the resulting heterogenous hardware also increases the challenge to ensure the security of these accelerators. High-Level Synthesis (HLS) automates the creation of a register transfer level (RTL) description of a digital circuit starting from its high-level specification (e.g., C/C++/SystemC). In this talk, I would like to discuss different extensions and methodologies to High-Level Synthesis (HLS) compilers for generating secure accelerators. Precisely addressing the HLS vulnerabilities like side-channel listed in Common Weakness Enumeration (CWE) list.

Babar khan

Talks and presentations